Datasheet

Table 12-71. Dual edge capture mode — edge polarity selection (continued)
ELSnB ELSnA Channel Port Enable Detected Edges
0 1 Enabled Rising edge
1 0 Enabled Falling edge
1 1 Enabled Rising and falling edges
Address: Base address + 5h offset + (3d × i), where i=0d to 5d
Bit 7 6 5 4 3 2 1 0
Read CHF
CHIE MSB MSA ELSB ELSA
0 0
Write 0
Reset
0 0 0 0 0 0 0 0
FTMx_CnSC field descriptions
Field Description
7
CHF
Channel Flag
Set by hardware when an event occurs on the channel. CHF is cleared by reading the CnSC register while
CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no effect; therefore,
CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to
the clearing sequence for a previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
6
CHIE
Channel Interrupt Enable
Enables channel interrupts.
0 Disable channel interrupts. Use software polling.
1 Enable channel interrupts.
5
MSB
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
the table in the register description.
MSB is write protected. It can be written only when MODE[WPDIS] = 1.
4
MSA
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
the table in the register description.
MSA is write protected. It can be written only when MODE[WPDIS] = 1.
3
ELSB
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See the table in the register
description.
ELSB is write protected. It can be written only when MODE[WPDIS] = 1.
2
ELSA
Edge or Level Select
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
302 Freescale Semiconductor, Inc.