Datasheet

output modes operation after normal execution resumes. Writes to the channel value
registers while BDM is active do not interfere with the partial completion of a coherency
sequence. After the write coherency mechanism has been fully exercised, the channel
value registers are updated using the buffered values while BDM was not active.
Address: Base address + 6h offset + (3d × i), where i=0d to 5d
Bit 7 6 5 4 3 2 1 0
Read
VAL_H
Write
Reset
0 0 0 0 0 0 0 0
FTMx_CnVH field descriptions
Field Description
7–0
VAL_H
Channel Value High Byte
Captured FTM counter value of the input capture function or the match value for the output modes
12.3.10 Channel Value Low (FTMx_CnVL)
See the description for the Channel Value High register.
Address: Base address + 7h offset + (3d × i), where i=0d to 5d
Bit 7 6 5 4 3 2 1 0
Read
VAL_L
Write
Reset
0 0 0 0 0 0 0 0
FTMx_CnVL field descriptions
Field Description
7–0
VAL_L
Channel Value Low Byte
Captured FTM counter value of the input capture function or the match value for the output modes
12.3.11 Counter Initial Value High (FTMx_CNTINH)
The Counter Initial Value registers contain the high and low bytes of the initial value for
the FTM counter.
Writing to either byte latches the value into a buffer. The registers are updated with the
value of their write buffer.
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
304 Freescale Semiconductor, Inc.