Datasheet

When BDM is active, the write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the counter initial value register are written while BDM is active. Any write to
the counter initial value registers bypasses the buffer latches and writes directly to the
counter initial value register while BDM is active.
The first time that the FTM clock is selected (first write to change the CLKS bits to a
non-zero value), FTM counter starts with the value 0x0000. To avoid this behavior,
before the first write to select the FTM clock, write the new value to the Counter Initial
Value registers and then initialize the FTM counter by writing any value to CNT).
Address: Base address + 17h offset
Bit 7 6 5 4 3 2 1 0
Read
INIT_H
Write
Reset
0 0 0 0 0 0 0 0
FTMx_CNTINH field descriptions
Field Description
7–0
INIT_H
Counter Initial Value High Byte
12.3.12 Counter Initial Value Low (FTMx_CNTINL)
See the description for the Counter Initial Value High register.
Address: Base address + 18h offset
Bit 7 6 5 4 3 2 1 0
Read
INIT_L
Write
Reset
0 0 0 0 0 0 0 0
FTMx_CNTINL field descriptions
Field Description
7–0
INIT_L
Counter Initial Value Low Byte
12.3.13 Capture and Compare Status (FTMx_STATUS)
STATUS contains a copy of the status flag CHnF bit, in CnSC, for each FTM channel for
software convenience.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 305