Datasheet

Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by reading
STATUS followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit.
Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF
interrupt request is not lost due to the clearing sequence for a previous CHF.
NOTE
The use of STATUS register is available only when
(MODE[FTMEN] = 1), (COMBINE = 1), and (CPWMS = 0).
The use of this register with (MODE[FTMEN] = 0),
(COMBINE = 0), or (CPWMS = 1) is not recommended and its
results are not guaranteed.
Address: Base address + 19h offset
Bit 7 6 5 4 3 2 1 0
Read CH7F CH6F CH5F CH4F CH3F CH2F CH1F CH0F
Write 0 0 0 0 0 0 0 0
Reset
0 0 0 0 0 0 0 0
FTMx_STATUS field descriptions
Field Description
7
CH7F
Channel 7 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
6
CH6F
Channel 6 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
5
CH5F
Channel 5 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
4
CH4F
Channel 4 Flag
See the register description.
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
306 Freescale Semiconductor, Inc.