Datasheet

FTMx_STATUS field descriptions (continued)
Field Description
0 No channel event has occurred.
1 A channel event has occurred.
3
CH3F
Channel 3 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
2
CH2F
Channel 2 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
1
CH1F
Channel 1 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
0
CH0F
Channel 0 Flag
See the register description.
0 No channel event has occurred.
1 A channel event has occurred.
12.3.14 Features Mode Selection (FTMx_MODE)
This register contains the control bits used to configure the fault interrupt and fault
control, capture test mode, PWM synchronization, write protection, channel output
initialization, and enable the enhanced features of the FTM. These controls relate to all
channels within this module.
Address: Base address + 1Ah offset
Bit 7 6 5 4 3 2 1 0
Read
FAULTIE FAULTM CAPTEST PWMSYNC WPDIS INIT FTMEN
Write
Reset
0 0 0 0 0 1 0 0
FTMx_MODE field descriptions
Field Description
7
FAULTIE
Fault Interrupt Enable
Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is
enabled.
Table continues on the next page...
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 307