Datasheet

FTMx_MODE field descriptions (continued)
Field Description
0 Fault control interrupt is disabled.
1 Fault control interrupt is enabled.
6–5
FAULTM
Fault Control Mode
Defines the FTM fault control mode.
FAULTM is write protected. These bits can be written only if MODE[WPDIS] = 1.
00 Fault control is disabled for all channels.
01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is
the manual fault clearing.
10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
4
CAPTEST
Capture Test Mode Enable
Enables the capture test mode. CAPTEST bit is write protected. This bit can be written only if WPDIS = 1.
0 Capture test mode is disabled.
1 Capture test mode is enabled.
3
PWMSYNC
PWM Synchronization Mode
Selects which triggers can be used by MOD, CV, CHnOM, and FTM counter synchronization (PWM
synchronization).
0 No restrictions. Software and hardware triggers can be used by MOD, CV, CHnOM, and FTM counter
synchronization.
1 Software trigger can be used only by MOD and CV synchronization, and hardware triggers can be
used only by CHnOM and FTM counter synchronization.
2
WPDIS
Write Protection Disable
When write protection is enabled (MODE[WPDIS] = 0), write protected bits can not be written. When write
protection is disabled (MODE[WPDIS] = 1), write protected bits can be written. The WPDIS bit is the
negation of the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is
read as a 1 and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
0 Write protection is enabled.
1 Write protection is disabled.
1
INIT
Initialize the Output Channels
When a 1 is written to INIT bit the output channels are initialized according to the state of their
corresponding bit in the OUTINIT register. Writing a 0 to INIT bit has no effect.
The INIT bit is always read as 0.
0
FTMEN
FTM Enable
This bit is write protected, and can be written only if WPDIS = 1.
0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not
use the FTM-specific registers.
1 All registers including the FTM-specific registers (second set of registers) are available for use with no
restrictions.
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
308 Freescale Semiconductor, Inc.