Datasheet

12.3.15 Synchronization (FTMx_SYNC)
This register configures the PWM synchronization.
A synchronization event can perform the synchronized update of MOD, CV, and
OUTMASK registers with the value of their write buffer and the FTM counter
initialization.
NOTE
The software trigger (SWSYNC bit) and hardware triggers
(TRIG0, TRIG1, and TRIG2 bits) have a potential conflict if
used together. Use only hardware or software triggers but not
both at the same time, otherwise unpredictable behavior is
likely to happen.
The selection of the boundary cycle (CNTMAX and CNTMIN
bits) is intended to provide the update of MOD, CNTIN, and
CV across all enabled channels simultaneously. The use of the
boundary cycle selection together with TRIG0, TRIG1, or
TRIG2 bits is likely to result in unpredictable behavior.
The MODE[PWMSYNC] bit determines which type of trigger
event controls the functions enabled by the SYNC register.
Address: Base address + 1Bh offset
Bit 7 6 5 4 3 2 1 0
Read
SWSYNC TRIG2 TRIG1 TRIG0 SYNCHOM REINIT CNTMAX CNTMIN
Write
Reset
0 0 0 0 0 0 0 0
FTMx_SYNC field descriptions
Field Description
7
SWSYNC
PWM Synchronization Software Trigger
Selects the software trigger as the PWM synchronization trigger. The software trigger occurs when a 1 is
written to SWSYNC bit.
0 Software trigger is not selected.
1 Software trigger is selected.
6
TRIG2
PWM Synchronization External Trigger 2
Selects external trigger 2 as the PWM synchronization trigger. External trigger 2 occurs when the FTM
detects a rising edge in the trigger 2 input signal.
Table continues on the next page...
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 309