Datasheet
FTMx_SYNC field descriptions (continued)
Field Description
0 External trigger 2 is not selected.
1 External trigger 2 is selected.
5
TRIG1
PWM Synchronization External Trigger 1
Selects external trigger 1 as the PWM synchronization trigger. External trigger 1 occurs when the FTM
detects a rising edge in the trigger 1 input signal.
0 External trigger 1 is not selected.
1 External trigger 1 is selected.
4
TRIG0
PWM Synchronization External Trigger 0
Selects external trigger 0 as the PWM synchronization trigger. External trigger 0 occurs when the FTM
detects a rising edge in the trigger 0 input signal.
0 External trigger 0 is not selected.
1 External trigger 0 is selected.
3
SYNCHOM
Output Mask Synchronization
Selects when the CHnOM bits in register OUTMASK are updated with the value of their write buffer.
0 CHnOM bits are updated with the value of the OUTMASK write buffer in all rising edges of the system
clock.
1 CHnOM bits are updated with the value of the OUTMASK write buffer only by the PWM
synchronization.
2
REINIT
FTM Counter Reinitialization by Synchronization (See “FTM Counter Synchronization”)
Determines if the FTM counter is reinitialized when the selected trigger for the synchronization is detected.
0 FTM counter continues to count normally.
1 FTM counter is updated with its initial value when the selected trigger is detected.
1
CNTMAX
Maximum Boundary Cycle Enable
Determines when the MOD, CNTIN, and CV registers are updated with their write buffer contents following
a PWM synchronization event. If CNTMAX is enabled, the registers are updated when the FTM counter
reaches its maximum value MOD.
0 The maximum boundary cycle is disabled.
1 The maximum boundary cycle is enabled.
0
CNTMIN
Minimum Boundary Cycle Enable
Determines when the MOD and CV registers are updated with their write buffer contents after a PWM
synchronization event. If CNTMIN is enabled, the registers are updated when the FTM counter reaches its
minimum value CNTIN.
0 The minimum boundary cycle is disabled.
1 The minimum boundary cycle is enabled.
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
310 Freescale Semiconductor, Inc.