Datasheet
NOTE
The channel (n) is the even channel and the channel (n+1) is the
odd channel of a pair of channels.
Address: Base address + 1Eh offset + (1d × i), where i=0d to 2d
Bit 7 6 5 4 3 2 1 0
Read 0
FAULTEN SYNCEN DTEN DECAP DECAPEN COMP COMBINE
Write
Reset
0 0 0 0 0 0 0 0
FTMx_COMBINEn field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
FAULTEN
Fault Control Enable
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
5
SYNCEN
Synchronization Enable
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
4
DTEN
Deadtime Enable
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
3
DECAP
Dual Edge Capture Mode Captures
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when MODE[FTMEN] = 1 and DECAPEN = 1.
DECAP bit is cleared automatically by hardware if dual edge capture one-shot mode is selected and when
the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
2
DECAPEN
Dual Edge Capture Mode Enable
Enables the dual edge capture mode in the channels (n) and (n+1). This bit reconfigures the function of
MSnA, ELSnB:ELSnA, and ELS(n+1)B:ELS(n+1)A bits in dual edge capture mode according to the table
Mode, Edge, and Level Selection in the description of the CnSC register.
This field applies only when MODE[FTMEN] = 1.
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
314 Freescale Semiconductor, Inc.