Datasheet

FTMx_POL field descriptions (continued)
Field Description
0
POL0
Channel 0 Polarity
Defines the polarity of the channel output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel polarity is active high.
1 The channel polarity is active low.
12.3.22 Fault Mode Status (FTMx_FMS)
This register contains the fault detection flags, write protection enable bit, and the logic
OR of the enable fault inputs.
Address: Base address + 25h offset
Bit 7 6 5 4 3 2 1 0
Read FAULTF
WPEN
FAULTIN 0 FAULTF3 FAULTF2 FAULTF1 FAULTF0
Write 0 0 0 0 0
Reset
0 0 0 0 0 0 0 0
FTMx_FMS field descriptions
Field Description
7
FAULTF
Fault Detection Flag
Represents the logic OR of the individual FAULTFn bits. Clear FAULTF by reading the FMS register while
FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition at the enabled fault
inputs. Writing a 1 to FAULTF has no effect.
If another fault condition is detected in an enabled fault input before the clearing sequence is completed,
the sequence is reset so FAULTF remains set after the clearing sequence is completed for the earlier fault
condition. FAULTF is also cleared when FAULTFn bits are cleared individually.
0 No fault condition was detected.
1 A fault condition was detected.
6
WPEN
Write Protection Enable
The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared
when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect.
0 Write protection is disabled. Write protected bits can be written.
1 Write protection is enabled. Write protected bits cannot be written.
5
FAULTIN
Fault Inputs
Represents the logic OR of the enabled fault input after its filter, if its filter is enabled, when fault control is
enabled.
0 The value of the fault input is 0.
1 The value of the fault input is 1.
Table continues on the next page...
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 319