Datasheet

12.3.24 Fault Input Filter Control (FTMx_FLTFILTER)
This register selects the fault inputs and enables the fault input filter.
Address: Base address + 28h offset
Bit 7 6 5 4 3 2 1 0
Read 0
FFVAL
Write
Reset
0 0 0 0 0 0 0 0
FTMx_FLTFILTER field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
FFVAL
Fault Input Filter
Selects the filter value for the fault inputs.
The fault filter is disabled when the value is zero.
NOTE: Writing to this field has immediate effect and must be done only when the fault control or the fault
input is disabled. Failure to do so could result in a missing fault detection.
12.3.25 Fault Input Control (FTMx_FLTCTRL)
This register selects the fault inputs and enables the fault input filter.
Address: Base address + 29h offset
Bit 7 6 5 4 3 2 1 0
Read
FFLTR3EN FFLTR2EN FFLTR1EN FFLTR0EN FAULT3EN FAULT2EN FAULT1EN FAULT0EN
Write
Reset
0 0 0 0 0 0 0 0
FTMx_FLTCTRL field descriptions
Field Description
7
FFLTR3EN
Fault Input 3 Filter Enable
Enables the filter for the fault input.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 Fault input filter is disabled.
1 Fault input filter is enabled.
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Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
322 Freescale Semiconductor, Inc.