Datasheet

12.4 Functional Description
The following sections describe the FTM features.
The notation used in this document to represent the counters and the generation of the
signals is shown in the following figure.
Channel (n) - high-true EPWM
FTM counter
0
3
4 0 1
2
3 4 0
1 2
3
4 0 1
2
0 0 0 0 0 0
1 1 1 1 1
1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
prescaler counter
channel (n) output
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
channel (n)
match
counter
overflow
PS[2:0] = 001
CNTINH:L = 0x0000
MODH:L = 0x0004
CnVH:L = 0x0002
Figure 12-186. Notation used
12.4.1 Clock Source
FTM module has only one clock domain that is the system clock.
12.4.1.1 Counter Clock Source
The CLKS[1:0] bits in the SC register select one of three possible clock sources for the
FTM counter or disable the FTM counter. After any MCU reset, CLKS[1:0] = 0:0 so no
clock source is selected.
The CLKS[1:0] bits may be read or written at any time. Disabling the FTM counter by
writing 0:0 to the CLKS[1:0] bits does not affect the FTM counter value or other
registers.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
324 Freescale Semiconductor, Inc.