Datasheet

• (CPWMS = 0)
• (CNTINH:L = 0x0000)
• (MODH:L = 0xFFFF)
In this case, the FTM counter runs free from 0x0000 through 0xFFFF and the TOF bit is
set when the FTM counter changes from 0xFFFF to 0x0000.
12.4.3.4 Counter reset
Any write to CNTH or CNTL register resets the FTM counter to the value of CNTINH:L
and the channels output to its initial value, except for channels in output compare mode.
The FTM counter synchronization can also be used to force the value of CNTINH:L into
the FTM counter and the channels output to its initial value, except for channels in output
compare mode.
12.4.4 Input capture mode
The input capture mode is selected when (DECAPEN = 0), (COMBINE = 0), (CPWMS
= 0), (MSnB:MSnA = 0:0), and (ELSnB:ELSnA ≠ 0:0).
When a selected edge occurs on the channel input, the current value of the FTM counter
is captured into the CnVH:L registers. At the same time, the CHnF bit is set and the
channel interrupt is generated if enabled by CHnIE = 1. See the following figure.
When a channel is configured for input capture, the CHn pin is an edge-sensitive input.
ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-capture
event. Note that the maximum frequency for the channel input signal to be detected
correctly is system clock divided by four, which is required to meet Nyquist criteria for
signal sampling.
When either half of the 16-bit capture register (CnVH:L) is read, the other half is latched
into a buffer to support coherent 16-bit access in big-endian or little-endian order. This
read coherency mechanism can be manually reset by writing to CnSC register.
Writes to the CnVH:L registers are ignored in input capture mode.
While in BDM, the input capture function works as configured. When a selected edge
event occurs, the FTM counter value, which is frozen because of BDM, is captured into
the CnVH:L registers and the CHnF bit is set.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
330 Freescale Semiconductor, Inc.