Datasheet

channel (n) input
synchronizer
1
is filter
enabled?
edge
detector
was falling
edge selected?
was rising
edge selected?
rising edge
falling edge
0
1
1
0
0 0
CnVH:L[15:0]
FTM counter
D Q
CLK
D Q
CLK
system clock
channel (n) interrupt
CHnIE
CHnF
Filter*
0
* NOTE: Filtering function is only available in the inputs of channel 0, 1, 2, and 3
Figure 12-193. Input capture mode
If the channel input does not have a filter enabled, then the input signal is always delayed
three rising edges of the system clock; that is, two rising edges to the synchronizer plus
one more rising edge to the edge detector. In other words, the CHnF bit is set on the third
rising edge of the system clock after a valid edge occurs on the channel input.
Note
• Input capture mode is available only with (CNTINH:L =
0x0000).
• Input capture mode with (CNTINH:L ≠ 0x0000) is not
recommended and its results are not guaranteed.
12.4.4.1 Filter for input capture mode
The filter function is available only on channels 0, 1, 2, and 3.
Firstly, the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block; see the following figure. When there is a state
change in the input signal, the 5-bit counter is reset and starts counting up. As long as the
new state is stable on the input, the counter continues to increment. If the 5-bit counter
overflows (the counter exceeds the value of the CHnFVAL[3:0] bits), the state change of
the input signal is validated. It is then transmitted as a pulse edge to the edge detector.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 331