Datasheet

system clock
5-bit up counter Logic to define
the filter output
filter output
divided by 4
channel (n) input after
the synchronizer
Logic to control
the filter counter
CHnFVAL[3:0]
C
S
Q
CLK
Figure 12-194. Channel input filter
If the opposite edge appears on the input signal before validation, the counter is reset. At
the next input transition, the counter starts counting again. Any pulse shorter than the
minimum valid width (CHnFVAL[3:0] bits × 4 system clocks) is regarded as a glitch and
is not passed on to the edge detector. A timing diagram of the input filter is shown in the
following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed three rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then
the input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system
clocks) plus a further four rising edges of the system clock (two rising edges to the
synchronizer, one rising edge to the filter output plus one more to the edge detector). In
other words, CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid
edge occurs on the channel input.
The clock for the 5-bit counter in the channel input filter is the system clock divided by 4.
CHnFVAL[3:0] = 0010
(binary value)
channel (n) input
after the synchronizer
5-bit counter
filter output
system clock divided by 4
Time
Figure 12-195. Channel input filter example
12.4.5 Output compare mode
The output compare mode is selected when (DECAPEN = 0), (COMBINE = 0),
(CPWMS = 0) and (MSnB:MSnA = 0:1).
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
332 Freescale Semiconductor, Inc.