Datasheet

It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnVH:CnVL registers, the CHnF bit is set and
the channel (n) interrupt is generated, if CHnIE = 1. However, the channel (n) output is
not modified and controlled by FTM.
Note
• Output compare mode is available only with
(CNTINH:CNTINL = 0x0000).
• Output compare mode with (CNTINH:CNTINL ≠ 0x0000)
is not recommended and its results are not guaranteed.
12.4.6 Edge-aligned PWM (EPWM) mode
The edge-aligned mode is selected when all of the following apply:
• (DECAPEN = 0)
• (COMBINE = 0)
• (CPWMS = 0)
• (MSnB = 1)
The EPWM period is determined by (MODH:L – CNTINH:L + 0x0001) and the pulse
width (duty cycle) is determined by (CnVH:L – CNTINH:L).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = CnVH:L), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
period
counter overflow counter overflow counter overflow
channel (n) output
channel (n) match channel (n) match
channel (n) match
pulse
width
Figure 12-199. EPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however,
the channel (n) output is not controlled by FTM.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
334 Freescale Semiconductor, Inc.