Datasheet

If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter
overflow, when the value of CNTINH:L is loaded into the FTM counter. Additionally, it
is forced low at the channel (n) match, when the FTM counter = CnVH:L. See the
following figure.
TOF bit
CHnF bit
CNTH:L
channel (n) output
MODH:L = 0x0008
CnVH:L = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1
2
3
4
5
6
7
8
0
1
2
...
previous value
Figure 12-200. EPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counter
overflow, when the value of CNTINH:L is loaded into the FTM counter. Additionally, it
is forced high at the channel (n) match, when the FTM counter = CnVH:L. See the
following figure.
TOF bit
CHnF bit
CNTH:L
channel (n) output
MODH:L = 0x0008
CnVH:L = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1
2
3
4
5
6
7
8
0
1
2
...
previous value
Figure 12-201. EPWM signal with ELSnB:ELSnA = X:1
If (CnVH:L = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and
CHnF bit is not set, even when there is the channel (n) match. If (CnVH:L > MODH:L),
then the channel (n) output is a 100% duty cycle EPWM signal and CHnF bit is not set,
even when there is the channel (n) match. Therefore, MODH:MODL must be less than
0xFFFF in order to get a 100% duty cycle EPWM signal.
Note
• EPWM mode is available only with (CNTINH:L =
0x0000).
• EPWM mode with (CNTINH:L ≠ 0x0000) is not
recommended and its results are not guaranteed.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 335