Datasheet

12.4.7 Center-aligned PWM (CPWM) mode
The center-aligned mode is selected when all of the following apply:
• (DECAPEN = 0)
• (COMBINE = 0)
• (CPWMS = 1)
The CPWM pulse width (duty cycle) is determined by 2 × (CnVH:L – CNTINH:L). The
period is determined by 2 × (MODH:L – CNTINH:L). See the following figure.
MODH:L must be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MODH:L and then
counts down until it reaches the value of CNTINH:L.
The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel
(n) match (FTM counter = CnVH:L) when the FTM counting is down, at the begin of the
pulse width, and when the FTM counting is up, at the end of the pulse width.
This type of PWM signal is called center-aligned because the pulse width centers for all
channels are aligned with the value of CNTINH:L.
The other channel modes are not compatible with the up-down counter (CPWMS = 1).
Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).
pulse width
counter overflow
FTM counter =
MODH:L
period
2 x (CnVH:L - CNTINH:L)
2 x (MODH:L - CNTINH:L)
FTM counter =
CNTINH:L
channel (n) match
(FTM counting
is down)
channel (n) match
(FTM counting
is up)
counter overflow
FTM counter =
MODH:L
channel (n) output
Figure 12-202. CPWM period and pulse width with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnVH:L registers,
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the
channel (n) output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)
match (FTM counter = CnVH:L) when counting down, and it is forced low at the channel
(n) match when counting up; see the following figure.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
336 Freescale Semiconductor, Inc.