Datasheet

TOF bit
...
7
8 8
7 7 7
6 6 6
5 5 54 43 3
2 21
0
1
...
previous value
CNTH:L
channel (n) output
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
channel (n) match in
down counting
counter
overflow
CHnF bit
MODH:L = 0x0008
CnVH:L = 0x0005
Figure 12-203. CPWM signal with ELSnB:ELSnA = 1:0
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)
match (FTM counter = CnVH:L) when counting down, and it is forced high at the
channel (n) match when counting up; see the following figure.
TOF bit
...
7
8 8
7 7 7
6 6 6
5 5 54 43 3
2 21
0
1
...
previous value
CNTH:L
channel (n) output
counter
overflow
channel (n) match in
down counting
channel (n) match in
up counting
channel (n) match in
down counting
counter
overflow
CHnF bit
MODH:L = 0x0008
CnVH:L = 0x0005
Figure 12-204. CPWM signal with ELSnB:ELSnA = X:1
If (CnVH:L = 0x0000) or (CnVH:L is a negative value, that is, CnVH[7] = 1) then the
channel (n) output is a 0% duty cycle CPWM signal and CHnF bit is not set even when
there is the channel (n) match.
If (CnVH:L is a positive value, that is, CnVH[7] = 0), (CnVH:L ≥ MODH:L), and
(MODH:L ≠ 0x0000), then the channel (n) output is a 100% duty cycle CPWM signal
and CHnF bit is not set even when there is the channel (n) match. This implies that the
usable range of periods set by MODH:L is 0x0001 through 0x7FFE, or 0x7FFF if you do
not need to generate a 100% duty cycle CPWM signal. This is not a significant limitation
because the resulting period is much longer than required for normal applications.
The CPWM mode must not be used when the FTM counter is a free running counter.
Note
• CPWM mode is available only with (CNTINH:L =
0x0000).
• CPWM mode with (CNTINH:L ≠ 0x0000) is not
recommended and its results are not guaranteed.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 337