Datasheet

12.4.8 Combine mode
The combine mode is selected when all of the following apply:
• (FTMEN = 1)
• (DECAPEN = 0)
• (COMBINE = 1)
• (CPWMS = 0)
In combine mode, the even channel (n) and adjacent odd channel (n+1) are combined to
generate a PWM signal in the channel (n) output.
In the combine mode, the PWM period is determined by (MODH:L – CNTINH:L +
0x0001) and the PWM pulse width (duty cycle) is determined by (|C(n+1)VH:L –
C(n)VH:L|).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = C(n)VH:L). The CH(n+1)F bit is set and the channel
(n+1) interrupt is generated (if CH(n+1)IE = 1) at the channel (n+1) match (FTM counter
= C(n+1)VH:C(n+1)VL).
If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of
the period (FTM counter = CNTINH:L) and at the channel (n+1) match (FTM counter =
C(n+1)VH:L). It is forced high at the channel (n) match (FTM counter = C(n)VH:L). See
the following figure.
If (ELSnB:ELSnA = X:1), then the channel (n) output is forced high at the beginning of
the period (FTM counter = CNTINH:L) and at the channel (n+1) match (FTM counter =
C(n+1)VH:L). It is forced low at the channel (n) match (FTM counter = C(n)VH:L). See
the following figure.
In combine mode, the ELS(n+1)B and ELS(n+1)A bits are not used in the generation of
the channels (n) and (n+1) output.
FTM counter
channel (n) match
channel (n+1) match
channel (n) output
with ELSnB:ELSnA = X:1
with ELSnB:ELSnA = 1:0
channel (n) output
Figure 12-205. Combine mode
The following figures illustrate the generation of PWM signals using combine mode.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
338 Freescale Semiconductor, Inc.