Datasheet

FTM counter
CNTINH:L
C(n+1)VH:L
not fully 0% duty cycle
channel (n) output
with ELSnB:ELSnA = 1:0
not fully 100% duty cycle
channel (n) output
with ELSnB:ELSnA = X:1
C(n)VH:L
MODH:L =
Figure 12-220. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD)
12.4.8.1 Asymmetrical PWM
In the combine mode, the control of the PWM signal first edge (when the channel (n)
match occurs, that is, FTM counter = C(n)VH:L) is independent of the control of the
PWM signal second edge (when the channel (n+1) match occurs, that is, FTM counter =
C(n+1)VH:L). So, the combine mode allows to generate asymmetrical PWM signals.
12.4.9 Complementary mode
The complementary mode is selected when all of the following apply:
• (FTMEN = 1)
• (DECAPEN = 0)
• (COMBINE = 1)
• (CPWMS = 0)
• (COMP = 1)
In complementary mode the channel (n+1) output is the inverse of the channel (n) output.
The channel (n+1) output is the same as the channel (n) output if all of the following
apply:
• (FTMEN = 1)
• (DECAPEN = 0)
• (COMBINE = 1)
• (CPWMS = 0)
• (COMP = 0)
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 345