Datasheet

FTM counter
channel (n+1) match
channel (n+1) output
with COMP = 1
channel (n+1) output
with COMP = 0
channel (n) output
with ELSnB:ELSnA = 1:0
channel (n) match
Figure 12-221. Channel (n+1) output in complementary mode with (ELSnB:ELSnA = 1:0)
FTM counter
channel (n+1) match
channel (n+1) output
with COMP = 1
channel (n+1) output
with COMP = 0
channel (n) output
with ELSnB:ELSnA = X:1
channel (n) match
Figure 12-222. Channel (n+1) output in complementary mode with (ELSnB:ELSnA = X:1)
12.4.10 Update of the registers with write buffers
This section describes the updating of registers that have write buffers.
12.4.10.1 CNTINH:L registers
CNTINH:L registers are always updated with their write buffer after both bytes have
been written.
12.4.10.2 MODH:L registers
If (CLKS[1:0] = 0:0), then MODH:L registers are updated when their second byte is
written, independent of FTMEN bit.
If (CLKS[1:0] ≠ 0:0 and FTMEN = 0), then MODH:L registers are updated according to
the CPWMS bit:
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
346 Freescale Semiconductor, Inc.