Datasheet

Note
• PWM synchronization boundary cycle is available only
when (CNTMIN = 1).
• PWM synchronization with (CNTMAX = 1) is not
recommended and its results are not guaranteed.
12.4.11.4 MODH:L registers synchronization
The MODH:L synchronization occurs when the MODH:L registers are updated with the
value of their write buffer.
The synchronization requires both bytes of MODH:L to have been written in one of the
following situations.
• If PWMSYNC = 0 and REINIT = 0, then the synchronization is made on the next
selected boundary cycle after an enabled trigger event takes place. If the trigger event
was a software trigger, then the SWSYNC bit is cleared on the next selected
boundary cycle. See the following figure.
SWSYNC bit
system clock
selected boundary cycle
MODH:L registers
are updated if both bytes
were written
software trigger event
write 1 to SWSYNC bit
Figure 12-225. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 0), and
software trigger was used
If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is
cleared when the trigger n event is detected. See the following figure.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 351