Datasheet

TRIG0 bit
system clock
MODH:L registers
are updated if both bytes
were written
trigger 0 event
write 1 to TRIG0 bit
Figure 12-228. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 1), and a
hardware trigger was used
• If PWMSYNC = 1, then the synchronization is made on the next selected boundary
cycle after the enabled software trigger event takes place. The SWSYNC bit is
cleared on the next selected boundary cycle. See the following figure.
SWSYNC bit
system clock
selected boundary cycle
MODH:L registers
are updated if both bytes
were written
software trigger event
write 1 to SWSYNC bit
Figure 12-229. MODH:L synchronization when (PWMSYNC = 1)
12.4.11.5 CnVH:L registers synchronization
The CnVH:L synchronization occurs when the CnVH:L registers are updated with the
value of their write buffer.
The synchronization requires both bytes of CnVH:L to have been written, SYNCEN = 1
and either a hardware or software trigger event as per MODH:L registers
synchronization.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 353