Datasheet

TRIG0 bit
system clock
CHnOM bit is updated and
TRIG0 bit is cleared
trigger 0 event
write 1 to TRIG0 bit
Figure 12-232. CHnOM synchronization when (SYNCHOM = 1), (PWMSYNC = 0), and a
hardware trigger was used
• If SYNCHOM = 1 and PWMSYNC = 1, then this synchronization is made on the
next enabled hardware trigger event. The trigger enable bit (TRIGn) is cleared when
the enabled hardware trigger n event is detected. See the following figure.
TRIG0 bit
system clock
CHnOM bit is updated and
TRIG0 bit is cleared
trigger 0 event
write 1 to TRIG0 bit
Figure 12-233. CHnOM Synchronization when (SYNCHOM = 1), (PWMSYNC = 1), and a
hardware trigger was used
12.4.11.7 FTM counter synchronization
The FTM counter synchronization occurs when the FTM counter is updated with the
value of the CNTINH:L registers and the channel outputs are forced to their initial value
as defined by the channel configuration.
• If REINIT = 0, then this synchronization is made when the FTM counter changes
from MODH:L to CNTINH:L.
• If REINIT = 1 and PWMSYNC = 0, then this synchronization is made on the next
enabled trigger event. If the trigger event was a software trigger, then the SWSYNC
bit is cleared. See the following figure.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 355