Datasheet

SWSYNC bit
system clock
FTM counter is reset and
channel outputs are forced to their initial value
software trigger event
write 1 to SWSYNC bit
Figure 12-234. FTM counter synchronization when (REINIT = 1), (PWMSYNC = 0), and
software trigger was used
If the trigger event was a hardware trigger, then the TRIGn bit is cleared. See the
following figure.
TRIG0 bit
system clock
FTM counter is reset and
channel outputs are forced to their initial value
trigger 0 event
write 1 to TRIG0 bit
Figure 12-235. FTM counter synchronization when (REINIT = 1), (PWMSYNC = 0), and a
hardware trigger was used
• If REINIT = 1 and PWMSYNC = 1, then this synchronization is made on the next
enabled hardware trigger event. The trigger enable bit (TRIGn) is cleared when the
enabled hardware trigger n event is detected. See the following figure.
TRIG0 bit
system clock
FTM counter is reset and
channel outputs are forced to their initial value
trigger 0 event
write 1 to TRIG0 bit
Figure 12-236. FTM counter synchronization when (REINIT = 1), (PWMSYNC = 1), and a
hardware trigger was used
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
356 Freescale Semiconductor, Inc.