Datasheet

Table 12-246. Summary of PWM synchronization (continued)
Register or bit
PWMSYN
C
REINIT
SYNCH
OM
CNTMA
X
CNTMI
N
SYNCE
N
Description
CnVH:L 0 0 X 1 0 1 CnVH:L are updated with their write
buffer contents when the counter
reaches its maximum value after the
enabled hardware or software
trigger has occurred.
0 0 X 0 1 1 CnVH:L are updated with their write
buffer contents when the counter
reaches its minimum value after the
enabled hardware or software
trigger has occurred.
0 1 X X X 1 CnVH:L are updated with their write
buffer contents when the enabled
hardware or software trigger occurs.
1 X X 1 0 1 CnVH:L are updated with their write
buffer contents when the counter
reaches its maximum value after the
enabled software trigger has
occurred.
1 X X 0 1 1 CnVH:L are updated with their write
buffer contents when the counter
reaches its minimum value after the
enabled software trigger has
occurred.
CNTH:L 0 1 X X X X CNTH:L are forced to the FTM
counter initial value when the
enabled hardware or software
trigger occurs.
1 1 X X X X CNTH:L are forced to the FTM
counter initial value when the
enabled hardware trigger occurs.
OUTMASK X X 0 X X X Changes to OUTMASK take effect
on the next rising edge of the
system clock.
0 X 1 X X X OUTMASK is updated with its write
buffer contents when the enabled
hardware or software trigger occurs.
1 X 1 X X X OUTMASK is updated with its write
buffer contents when the enabled
hardware trigger occurs.
Table continues on the next page...
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
358 Freescale Semiconductor, Inc.