Datasheet

Table 12-246. Summary of PWM synchronization (continued)
Register or bit
PWMSYN
C
REINIT
SYNCH
OM
CNTMA
X
CNTMI
N
SYNCE
N
Description
SWSYNC bit 0 0 X 1 0 X SWSYNC bit is cleared when the
counter reaches its maximum value
after the enabled software trigger
has occurred.
0 0 X 0 1 X SWSYNC bit is cleared when the
counter reaches its minimum value
after the enabled software trigger
has occurred.
0 1 X X X X SWSYNC bit is cleared when the
enabled software trigger occurs.
1 X X 1 0 X SWSYNC bit is cleared when the
counter reaches its maximum value
after the enabled software trigger
has occurred.
1 X X 0 1 X SWSYNC bit is cleared when the
counter reaches its minimum value
after the enabled software trigger
has occurred.
TRIGn bit X X X X X X TRIGn bit is cleared when the
enabled hardware trigger has
occurred.
12.4.12 Deadtime insertion
The deadtime insertion is enabled when (DTEN = 1) and (DTVAL[5:0] is non- zero).
DEADTIME register defines the deadtime delay that can be used for all FTM channels.
The DTPS[1:0] bits define the prescaler for the system clock and the DTVAL[5:0] bits
define the deadtime modulo; that is, the number of deadtime prescaler clocks).
The deadtime delay insertion ensures that no two complementary signals (channel (n) and
(n+1)) drive the active state at the same time.
For POL(n) = 0, POL(n+1) = 0, and deadtime enabled, a rising edge on the output of
channel (n) remains low for the duration of the deadtime delay, after which the rising
edge appears on the output. Similarly, when a falling edge is due on the output of channel
(n), the channel (n+1) output remains low for the duration of the deadtime delay, after
which the channel (n+1) output will have a rising edge.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 359