Datasheet

For POL(n) = 1, POL(n+1) = 1, and deadtime enabled, a falling edge on the output of
channel (n) remains high for the duration of the deadtime delay, after which the falling
edge appears on the output. Similarly, when a rising edge is due on the output of channel
(n), the channel (n+1) output remains high for the duration of the deadtime delay, after
which the channel (n+1) output will have a falling edge.
FTM counter
channel (n+1) match
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 12-237. Deadtime insertion with ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) =
0
FTM counter
channel (n+1) match
channel (n) output
(before deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
channel (n) match
Figure 12-238. Deadtime insertion with ELSnB:ELSnA = X:1, POL(n) = 0, and POL(n+1) =
0
NOTE
Deadtime feature is available only in combine and
complementary modes.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
360 Freescale Semiconductor, Inc.