Datasheet

12.4.12.1 Deadtime insertion corner cases
If (PS[2:0] bits are cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1):
• and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n
+1)VH:L – C(n)VH:L) × system clock), then the channel (n) output is always the
inactive value (POL(n) bit value).
• and the deadtime delay is greater than or equal to the channel (n+1) duty cycle
((MODH:L – CNTINH:L + 1 – (C(n+1)VH:L – C(n)VH:L) ) × system clock), then
the channel (n+1) output is always the inactive value (POL(n+1) bit value).
Although in most cases the deadtime delay is not comparable to channels (n) and (n+1)
duty cycle, the following figures show examples where the deadtime delay is comparable
to the duty cycle.
FTM counter
channel (n+1) match
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 12-239. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and
POL(n+1) = 0) when the deadtime delay is comparable to channel (n+1) duty cycle
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 361