Datasheet

FTM counter
channel (n+1) match
channel (n) match
channel (n) output
(before deadtime
insertion)
channel (n) output
(after deadtime
insertion)
channel (n+1) output
(before deadtime
insertion)
channel (n+1) output
(after deadtime
insertion)
Figure 12-240. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and
POL(n+1) = 0) when the deadtime delay Is comparable to channels (n) and (n+1) duty
cycle
12.4.13 Output mask
The output mask register OUTMASK can be used to force channel outputs to their
inactive state through software; for example, to control a BLDC motor.
Any write to a CHnOM bit updates the OUTMASK write buffer. The CHnOM bit is
updated with the value of its corresponding bit in the OUTMASK write buffer according
to OUTMASK register synchronization.
If CHnOM = 1, then the channel (n) output is forced to its inactive state, defined by the
POLn bit in register POL. If CHnOM = 0, then the channel (n) output is unaffected by the
output mask function.
When a CHnOM bit is cleared, the channel (n) output is enabled. See the following
figure.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
362 Freescale Semiconductor, Inc.