Datasheet

is reset and starts counting up. As long as the new state is stable on the fault input n, the
counter continues to increment. If the 5-bit counter overflows and exceeds the value of
the FFVAL[3:0] bits, the new fault input n value is validated. It is then transmitted as a
pulse edge to the edge detector.
If the opposite edge appears on the fault input n signal before validation (counter
overflow), the counter is reset. At the next input transition, the counter starts counting
again. Any pulse that is shorter than the minimum value selected by FFVAL[3:0] bits (×
system clock) is regarded as a glitch and is not passed on to the edge detector.
The fault input n filter is disabled when the FFVAL[3:0] bits are zero or when
FAULTnEN = 0. In this case the fault input n signal is delayed two rising edges of the
system clock and the FAULTFn bit is set on the third rising edge of the system clock
after a rising edge occurs on the fault input n.
If FFVAL[3:0] ≠ 0000 and FAULTnEN = 1, then the fault input n signal is delayed (3 +
FFVAL[3:0]) rising edges of the system clock; that is, the FAULTFn bit is set (4 +
FFVAL[3:0]) rising edges of the system clock after a rising edge occurs on the fault input
n.
fault input n*
system clock
* where n = 3, 2, 1, 0
synchronizer
fault input n* value
rising edge
FAULTFn*
0000)
and (FFLTRnEN*)
0
1
edge
detector
fault input
polarity
control
Fault filter
(5-bit counter)
CLK
CLK
D D
Q
Q
FLTnPOL
(FFVAL[3:0]
Figure 12-242. Fault input n control block diagram
If the fault control and fault input n are enabled and a rising edge at the fault input n
signal is detected, then the FAULTFn bit is set. The FAULTF bit is the logic OR of
FAULTFn[3:0] bits. See the following figure.
fault interrupt
FAULTIE
FAULTIN
fault input 0 value
fault input 1 value
fault input 2 value
fault input 3 value
FAULTF
FAULTF0
FAULTF1
FAULTF2
FAULTF3
Figure 12-243. FAULTF and FAULTIN bits and fault interrupt
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
364 Freescale Semiconductor, Inc.