Datasheet

If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred
(rising edge at the logic OR of the enabled fault input) and (FAULTEN = 1), then
channel (n) and (n+1) outputs are forced to their safe value (that is, the channel (n) output
is forced to the value of POL(n) and the channel (n+1) is forced to the value of POL(n
+1)).
The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1). This interrupt
request remains set until:
• Software clears the FAULTF bit (by reading FAULTF bit as 1 and writing 0 to it)
• Software clears the FAULTIE bit
• A reset occurs
Note
Fault control is available only in combine mode.
12.4.14.1 Automatic fault clearing
If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the disabled
channel outputs are enabled when the fault input signal (FAULTIN) returns to zero and a
new PWM cycle begins. See the following figure.
FTM counter
channel (n) output
(before fault control)
FAULTIN bit
channel (n) output
(after fault control with
automatic fault clearing
and POLn=0)
the beginning of new PWM cycles
FAULTF bit
FAULTF bit is cleared
Figure 12-244. Fault control with automatic fault clearing
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 365