Datasheet

Note
Polarity control is available only in combine mode.
12.4.16 Initialization
The initialization forces the CHnOI bit value to the channel (n) output when a one is
written to the INIT bit.
Note
• It is recommended to use the initialization only when the
FTM counter is disabled (CLKS[1:0] = 0:0).
• Initialization is available only in combine mode.
12.4.17 Features priority
The following figure shows the priority of the features that can be combined to generate
channel (n) and (n+1) outputs.
(generation of channels
in Output Compare, EPWM,
CPWM, Combine and/or
Complementary modes)
(n) and (n 1) output
Deadtime
Insertion
Initialization
Fault
Control
Polarity
Control
Output
Mask
channel (n) output
channel (n
Output modes logic
1) output
Figure 12-246. FTM features priority
12.4.18 Channel trigger output
The channel trigger output is generated if (FTMEN = 1) and one or more channels were
selected by the CHjTRIG bit, where j = 0, 1, 2, 3, 4, or 5. The CHjTRIG bit defines if the
channel (j) match (that is, FTM counter = C(j)VH:L) generates the trigger.
The channel trigger output provides a trigger signal that is used for on-chip modules.
The FTM is able to generate multiple triggers in one PWM period. Because each trigger
is generated for a specific channel, several channels are required to implement this
functionality. This behavior is described in the following figure.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 367