Datasheet

• ICSCLK(BUS) — This up to 20 MHz clock source is used as the bus clock that is
the reference to CPU and all peripherals. Control bits in the ICS control registers
determine which of three clock sources is connected:
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) output
• ICSLCLK — This clock source is derived from the digitally controlled oscillator
(DCO) of the ICS when the ICS is configured to run off of the internal or external
reference clock. Development tools can select this internal self-clocked source (8
MHz) to speed up BDC communications in systems where the bus clock is slow.
• ICSIRCLK — This is the internal reference clock and can be selected as the clock
source to the WDOG module.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being
synchronized to the bus clock. It can be selected as clock source to the FTM and
MTIM modules. The frequency of the ICSFFCLK is determined by the setting of the
ICS.
• LPOCLK — This clock is generated from an internal low power oscillator (≈1 kHz)
that is completely independent of the ICS module. The LPOCLK can be selected as
the clock source to the RTC or WDOG modules.
• OSCOUT — This is the direct output of the external oscillator module and can be
selected as the clock source for RTC, WDOG and ADC.
• TCLK0 — This is an optional external clock source for the FTM0 and MTIM0
modules. The TCLK0 must be limited to 1/4th frequency of the bus clock for
synchronization.
• TCLK1 — This is an optional external clock source for the FTM1 and MTIM1
modules. The TCLK1 must be limited to 1/4th frequency of the bus clock for
synchronization.
• TCLK2 — This is an optional external clock source for the FTM2 module. The
TCLK2 must be limited to 1/4th frequency of the bus clock for synchronization.
Chapter 1 Device Overview
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 37