Datasheet

Note
Initialization trigger is available only in combine mode.
12.4.20 Capture test mode
The capture test mode allows the testing of the CnVH:L registers, the FTM counter, and
the interconnection logic between the FTM counter and CnVH:L registers.
In this test mode, all channels must be configured for input capture mode (see Input
capture mode) and FTM counter must be configured for up-counting (see Up counting).
When the capture test mode is enabled (CAPTEST = 1), the FTM counter is frozen and
any write to CNTH and CNTL updates directly the FTM counter; see the following
figure. After both bytes were written, independent of the order, all CnVH:L registers are
updated with the value that was written to CNTH:L registers and CHnF bits are set.
Therefore, the FTM counter is updated with its next value according to its configuration.
Its next value depends on CNTINH:L, MODH:L, and the value that was written to FTM
counter.
The next reads of CnVH:L registers return the value that was written to FTM counter and
the next reads of CNTH:L register return the next value of the FTM counter.
The read coherency mechanism of CNTH:L and CnVH:L registers remains enabled.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
370 Freescale Semiconductor, Inc.