Datasheet

12.4.22 TPM emulation
This section describe the FTM features that are selected according to the FTMEN bit.
12.4.22.1 MODH:L and CnVH:L synchronization
If (FTMEN = 0), then the MODH:L and CnVH:L registers are updated according to the
Update of the registers with write buffers and they are not updated by PWM
synchronization.
If (FTMEN = 1), then the MODH:L and CnVH:L registers are updated only by PWM
synchronization (PWM synchronization).
12.4.22.2 Free running counter
If (FTMEN = 0), then the FTM counter is a free running counter when (MODH:L =
0x0000) or (MODH:L = 0xFFFF).
If (FTMEN = 1), then the FTM counter is a free running counter when (CPWMS = 0),
(CNTINH:L = 0x0000), and (MODH:L = 0xFFFF).
12.4.22.3 Write to SC
If (FTMEN = 0), then a write to the SC register resets the write coherency mechanism of
MODH:L registers.
If (FTMEN = 1), then a write to the SC register does not reset the write coherency
mechanism of MODH:L registers.
12.4.22.4 Write to CnSC
If (FTMEN = 0), then a write to the CnSC register resets the write coherency mechanism
of CnVH:L registers.
If (FTMEN = 1), then a write to the CnSC register does not reset the write coherency
mechanism of CnVH:L registers.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
380 Freescale Semiconductor, Inc.