Datasheet

12.4.23 BDM mode
When BDM mode is active, the FlexTimer counter and the channels output are frozen.
However, the value of FlexTimer counter or the channels output are modified in BDM
mode when:
• A write of any value to the CNTH or CNTL registers (Counter reset) resets the FTM
counter to the value of CNTINH:L and the channels output to their initial value,
except for channels in output compare mode.
• The PWM synchronization with REINIT = 1 (see FTM counter synchronization)
resets the FTM counter to the value of CNTINH:L registers and the channels output
to their initial value, except for channels in output compare mode.
• The initialization (Initialization) forces the value of the CHnOI bit to the channel (n)
output.
Note
Do not use the above cases together with fault control (Fault
control). If fault control is enabled and the fault condition is at
the enabled fault input, these cases reset the FTM counter to the
CNTINH:L value and the channels output to their initial value.
12.5 Reset overview
The FTM is reset whenever any chip reset occurs.
When the FTM exits from reset:
• The FTM counter and the prescaler counter are zero and are stopped (CLKS[1:0] =
0b00)
• The timer overflow interrupt is zero (Timer overflow interrupt)
• The channels interrupts are zero (Channel (n) interrupt)
• The fault interrupt is zero (Fault interrupt)
• The channels are in input capture mode (Input capture mode)
• The channels outputs are zero
• The channels pins are not controlled by FTM (ELS(n)B:ELS(n)A = 0b00). See table
"Mode, Edge, and Level Selection"
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 381