Datasheet

The following figure shows the FTM behavior after the reset. At the reset (item 1), the
FTM counter is disabled (see table "FTM Clock Source Selection"), its value is updated
to zero and the pins are not controlled by FTM (table "Mode, Edge, and Level
Selection").
After the reset, the FTM should be configured (item 2). It is necessary to define the FTM
counter mode, the FTM counting limits (MODH:L and CNTINH:L registers value), the
channels mode and CnVH:L registers value according to the channels mode.
Because of this, you should write any value to CNTH or CNTL registers (item 3). This
write updates the FTM counter with the value of CNTINH:L and the channels output
with its initial value (except for channels in output compare mode) (Counter reset).
The next step is to select the FTM counter clock by the CLKS[1:0] bits (item 4). It is
important to highlight that the pins are controlled only by FTM when CLKS[1:0] bits are
different from zero (table "Mode, Edge, and Level Selection").
(1) FTM reset
. . .
0x0016
0x0015
0x0014
0x0013
0x00110x0010
0x0018
0x0017
XXXX 0x0000
0x0012
FTM counter
CLKS[1:0]
(4) write 0b01 to CLKS[1:0]
(3) write any value to
CNTH or CNTL registers
(2) FTM configuration
channel (n) pin is controlled by FTM
Note
– CNTINH:L = 0x0010
– Channel (n) is in low-true combine mode with CNTINH:L < C(n)VH:L < C(n+1)VH:L < MODH:L
– C(n)VH:L = 0x0015
0b00
XX
0b01
channel (n) output
Figure 12-259. FTM behavior after the reset when the channel (n) is in combine mode
The following figure shows an example when the channel (n) is in output compare mode
and the channel (n) output is toggled when there is a match. In the output compare mode,
the channel output is not updated to its initial value when there is a write to CNTH or
CNTL registers (item 3). In this case, it is recommended to use the initialization
(Initialization) to update the channel output to the selected value (item 4).
Reset overview
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
382 Freescale Semiconductor, Inc.