Datasheet

13.5 External signal description
The MTIM includes one external signal, TCLK, used to input an external clock when
selected as the MTIM clock source. The signal properties of TCLK are shown in the
following table.
Table 13-1. MTIM external signal
Signal Function I/O
TCLK External clock source input into MTIM I
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle
and clock jitter must be accommodated. Therefore, the TCLK signal must be limited to
one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin.
13.6 Register definition
MTIM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
18 MTIM Status and Control Register (MTIM0_SC) 8 R/W 10h 13.6.1/388
19 MTIM Clock Configuration Register (MTIM0_CLK) 8 R/W 00h 13.6.2/389
1A MTIM Counter Register (MTIM0_CNT) 8 R 00h 13.6.3/390
1B MTIM Modulo Register (MTIM0_MOD) 8 R/W 00h 13.6.4/390
1C MTIM Status and Control Register (MTIM1_SC) 8 R/W 10h 13.6.1/388
1D MTIM Clock Configuration Register (MTIM1_CLK) 8 R/W 00h 13.6.2/389
1E MTIM Counter Register (MTIM1_CNT) 8 R 00h 13.6.3/390
1F MTIM Modulo Register (MTIM1_MOD) 8 R/W 00h 13.6.4/390
Chapter 13 8-bit modulo timer (MTIM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 387