Datasheet

SCIx_C2 field descriptions (continued)
Field Description
TE must be 1 to use the SCI transmitter. When TE is set, the SCI forces the TxD pin to act as an output
for the SCI system.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction
of traffic on the single SCI communication line (TxD pin).
TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or
queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
0 Transmitter off.
1 Transmitter on.
2
RE
Receiver Enable
When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS is set
the RxD pin reverts to being a general-purpose I/O pin even if RE is set.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control
This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic
hardware detection of a selected wakeup condition. The wakeup condition is an idle line between
messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE =
1, address-mark wakeup. Application software sets RWU and, normally, a selected hardware condition
automatically clears RWU.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break
Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 or 12, 13 or 14 or 15 if BRK13 = 1, bit times of logic 0 are queued as long as SBK is
set. Depending on the timing of the set and clear of SBK relative to the information currently being
transmitted, a second break character may be queued before software clears SBK.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
15.2.5 SCI Status Register 1 (SCIx_S1)
This register has eight read-only status flags. Writes have no effect. Special software
sequences, which do not involve writing to this register, clear these status flags.
Address: Base address + 4h offset
Bit 7 6 5 4 3 2 1 0
Read TDRE TC RDRF IDLE OR NF FE PF
Write
Reset
1 1 0 0 0 0 0 0
Register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
410 Freescale Semiconductor, Inc.