Datasheet
15.2.7 SCI Control Register 3 (SCIx_C3)
Address: Base address + 6h offset
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset
0 0 0 0 0 0 0 0
SCIx_C3 field descriptions
Field Description
7
R8
Ninth Data Bit for Receiver
When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the
left of the msb of the buffered data in the SCI_D register. When reading 9-bit data, read R8 before reading
SCI_D because reading SCI_D completes automatic flag clearing sequences that could allow R8 and
SCI_D to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter
When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit data bit to the
left of the msb of the data in the SCI_D register. When writing 9-bit data, the entire 9-bit value is
transferred to the SCI shift register after SCI_D is written so T8 should be written, if it needs to change
from its previous value, before SCI_D is written. If T8 does not need to change in the new value, such as
when it is used to generate mark or space parity, it need not be written each time SCI_D is written.
5
TXDIR
TxD Pin Direction in Single-Wire Mode
When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines
the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
4
TXINV
Transmit Data Inversion
Setting this bit reverses the polarity of the transmitted data output.
NOTE: Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
0 Transmit data not inverted.
1 Transmit data inverted.
3
ORIE
Overrun Interrupt Enable
This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled; use polling.
1 Hardware interrupt requested when OR is set.
2
NEIE
Noise Error Interrupt Enable
This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled; use polling).
1 Hardware interrupt requested when NF is set.
Table continues on the next page...
Register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
414 Freescale Semiconductor, Inc.