Datasheet

soon as the shifter is available. If SCI_C2[SBK] remains 1 when the queued break moves
into the shifter, synchronized to the baud rate clock, an additional break character is
queued. If the receiving device is another Freescale Semiconductor SCI, the break
characters are received as 0s in all eight data bits and a framing error (SCI_S1[FE] = 1)
occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between
messages to wake up any sleeping receivers. Normally, a program would wait for
SCI_S1[TDRE] to become set to indicate the last character of a message has moved to
the transmit shifter, then write 0 and then write 1 to the SCI_C2[TE] bit. This action
queues an idle character to be sent as soon as the shifter is available. As long as the
character in the shifter does not finish while SCI_C2[TE] is cleared, the SCI transmitter
never actually releases control of the TxD pin. If there is a possibility of the shifter
finishing while SCI_C2[TE] is cleared, set the general-purpose I/O controls so the pin
shared with TxD is an output driving a logic 1. This ensures that the TxD line looks like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1
to SCI_C2[TE].
The length of the break character is affected by the SCI_S2[BRK13] and SCI_C1[M] bits
as shown below.
Table 15-37. Break character length
BRK13 M SBNS Break character length
0 0 0 10 bit times
0 0 1 11 bit times
0 1 0 11 bit times
0 1 1 12 bit times
1 0 0 13 bit times
1 0 1 14 bit times
1 1 0 14 bit times
1 1 1 15 bit times
15.3.3 Receiver functional description
In this section, the receiver block diagram is a guide for the overall receiver functional
description. Next, the data sampling technique used to reconstruct receiver data is
described in more detail. Finally, two variations of the receiver wakeup function are
explained.
Functional description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
418 Freescale Semiconductor, Inc.