Datasheet

The falling edge detection logic continuously looks for falling edges. If an edge is
detected, the sample clock is resynchronized to bit times. This improves the reliability of
the receiver in the presence of noise or mismatched baud rates. It does not improve worst
case analysis because some characters do not have any extra falling edges anywhere in
the character frame.
In the case of a framing error, provided the received character was not a break character,
the sampling logic that searches for a falling edge is filled with three logic 1 samples so
that a new start bit can be detected almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters
until the framing error flag is cleared. The receive shift register continues to function, but
a complete character cannot transfer to the receive data buffer if SCI_S1[FE] remains set.
15.3.3.2 Receiver wakeup operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the
characters in a message intended for a different SCI receiver. In such a system, all
receivers evaluate the first character(s) of each message, and as soon as they determine
the message is intended for a different receiver, they write logic 1 to the receiver wake up
control bit(SCI_C2[RWU]). When RWU bit is set, the status flags associated with the
receiver, with the exception of the idle bit, IDLE, when SCI_S2[RWUID] bit is set, are
inhibited from setting, thus eliminating the software overhead for handling the
unimportant message characters. At the end of a message, or at the beginning of the next
message, all receivers automatically force SCI_C2[RWU] to 0 so all receivers wake up in
time to look at the first character(s) of the next message.
15.3.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
SCI_C2[RWU] is cleared automatically when the receiver detects a full character time of
the idle-line level. The SCI_C1[M] control bit selects 8-bit or 9-bit data mode and the
SCI_BDH[SBNS] bit selects 1-bit or 2-bit stop bit number that determines how many bit
times of idle are needed to constitute a full character time, 10 or 11 or 12 bit times
because of the start and stop bits.
When SCII_C2[RWU] is one and SCI_S2[RWUID] is zero, the idle condition that wakes
up the receiver does not set the SCI_S1[IDLE] flag. The receiver wakes up and waits for
the first data character of the next message that sets the SCI_S1[RDRF] flag and
generates an interrupt if enabled. When SCI_S2[RWUID] is one, any idle condition sets
the SCI_S1[IDLE] flag and generates an interrupt if enabled, regardless of whether
SCI_C2[RWU] is zero or one.
Functional description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
420 Freescale Semiconductor, Inc.