Datasheet

The idle-line type (SCI_C1[ILT]) control bit selects one of two ways to detect an idle
line. When SCI_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop
bit and any logic 1s at the end of a character count toward the full character time of idle.
When SCI_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so
the idle detection is not affected by the data in the last character of the previous message.
15.3.3.2.2 Address-mark wakeup
When wake is set, the receiver is configured for address-mark wakeup. In this mode,
SCI_C2[RWU] is cleared automatically when the receiver detects a, or two, if
SCI_BDH[SBNS] = 1, logic 1 in the most significant bits of a received character, eighth
bit when SCI_C1[M] is cleared and ninth bit when SCI_C1[M] is set.
Address-mark wakeup allows messages to contain idle characters, but requires the msb
be reserved for use in address frames. The one, or two, if SCI_BDH[SBNS] = 1, logic 1s
msb of an address frame clears the SCI_C2[RWU] bit before the stop bits are received
and sets the SCI_S1[RDRF] flag. In this case, the character with the msb set is received
even though the receiver was sleeping during most of this character time.
15.3.4 Interrupts and status flags
The SCI system has three separate interrupt vectors to reduce the amount of software
needed to isolate the cause of the interrupt. One interrupt vector is associated with the
transmitter for SCI_S1[TDRE] and SCI_S1[TC] events. Another interrupt vector is
associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF events. A third
vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt
sources can be separately masked by local interrupt enable masks. The flags can be
polled by software when the local masks are cleared to disable generation of hardware
interrupt requests.
The SCI transmitter has two status flags that can optionally generate hardware interrupt
requests. Transmit data register empty (SCI_S1[TDRE]) indicates when there is room in
the transmit data buffer to write another transmit character to SCI_D. If the transmit
interrupt enable (SCI_C2[TIE]) bit is set, a hardware interrupt is requested when
SCI_S1[TDRE] is set. Transmit complete (SCI_S1[TC]) indicates that the transmitter is
finished transmitting all data, preamble, and break characters and is idle with TxD at the
inactive level. This flag is often used in systems with modems to determine when it is
safe to turn off the modem. If the transmit complete interrupt enable (SCI_C2[TCIE]) bit
is set, a hardware interrupt is requested when SCI_S1[TC] is set. Instead of hardware
Chapter 15 Serial communications interface (SCI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 421