Datasheet

Register Definition
The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status,
to hold an SPI data match value, and for transmit/receive data.
SPI memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3098 SPI control register 1 (SPI0_C1) 8 R/W 04h 16.3.1/430
3099 SPI control register 2 (SPI0_C2) 8 R/W 00h 16.3.2/432
309A SPI baud rate register (SPI0_BR) 8 R/W 00h 16.3.3/433
309B SPI status register (SPI0_S) 8 R 20h 16.3.4/434
309D SPI data register (SPI0_D) 8 R/W 00h 16.3.5/435
309F SPI match register (SPI0_M) 8 R/W 00h 16.3.6/436
16.3.1 SPI control register 1 (SPIx_C1)
This read/write register includes the SPI enable control, interrupt enables, and
configuration options.
Address: 3098h base + 0h offset = 3098h
Bit 7 6 5 4 3 2 1 0
Read
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Write
Reset
0 0 0 0 0 1 0 0
SPI0_C1 field descriptions
Field Description
7
SPIE
SPI interrupt enable: for SPRF and MODF
This bit enables the interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events.
0 Interrupts from SPRF and MODF are inhibited—use polling
1
Request a hardware interrupt when SPRF or MODF is 1
6
SPE
SPI system enable
This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is
cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
Table continues on the next page...
16.3
Register Definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
430 Freescale Semiconductor, Inc.