Datasheet

16.3.2 SPI control register 2 (SPIx_C2)
This read/write register is used to control optional features of the SPI system. Bit 6 is not
implemented and always reads 0.
Address: 3098h base + 1h offset = 3099h
Bit 7 6 5 4 3 2 1 0
Read
SPMIE
0
Reserved MODFEN BIDIROE Reserved SPISWAI SPC0
Write
Reset
0 0 0 0 0 0 0 0
SPI0_C2 field descriptions
Field Description
7
SPMIE
SPI match interrupt enable
This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.
0 Interrupts from SPMF inhibited (use polling)
1 When SPMF is 1, requests a hardware interrupt
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
Reserved
This field is reserved.
Do not write to this reserved bit.
4
MODFEN
Master mode-fault function enable
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave
select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the
description of the SSOE bit in the C1 register.
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3
BIDIROE
Bidirectional mode output enable
When bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, the BIDIROE bit
determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending
on whether the SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin,
respectively, as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
2
Reserved
This field is reserved.
Do not write to this reserved bit.
1
SPISWAI
SPI stop in wait mode
This bit is used for power conservation while the device is in wait mode.
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
Table continues on the next page...
Register Definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
432 Freescale Semiconductor, Inc.