Datasheet

SPI0_C2 field descriptions (continued)
Field Description
0
SPC0
SPI pin control 0
This bit enables bidirectional pin configurations.
0 SPI uses separate pins for data input and data output (pin mode is normal).
In master mode of operation: MISO is master in and MOSI is master out.
In slave mode of operation: MISO is slave out and MOSI is slave in.
1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional).
In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or
master I/O when BIDIROE is 1.
In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1;
MOSI is not used by SPI.
16.3.3 SPI baud rate register (SPIx_BR)
Use this register to set the prescaler and bit rate divisor for an SPI master. This register
may be read or written at any time.
Address: 3098h base + 2h offset = 309Ah
Bit 7 6 5 4 3 2 1 0
Read 0
SPPR[2:0] SPR[3:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI0_BR field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
SPPR[2:0]
SPI baud rate prescale divisor
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is
the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider.
Refer to the description of “SPI Baud Rate Generation” for details.
000 Baud rate prescaler divisor is 1
001 Baud rate prescaler divisor is 2
010 Baud rate prescaler divisor is 3
011 Baud rate prescaler divisor is 4
100 Baud rate prescaler divisor is 5
101 Baud rate prescaler divisor is 6
110 Baud rate prescaler divisor is 7
111 Baud rate prescaler divisor is 8
Table continues on the next page...
Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 433