Datasheet

SPI0_BR field descriptions (continued)
Field Description
3–0
SPR[3:0]
SPI baud rate divisor
This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes
from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
0000 Baud rate divisor is 2
0001 Baud rate divisor is 4
0010 Baud rate divisor is 8
0011 Baud rate divisor is 16
0100 Baud rate divisor is 32
0101 Baud rate divisor is 64
0110 Baud rate divisor is 128
0111 Baud rate divisor is 256
1000 Baud rate divisor is 512
All others Reserved
16.3.4 SPI status register (SPIx_S)
This register contains read-only status bits. Writes have no meaning or effect.
NOTE
Bits 3 through 0 are not implemented and always read 0.
Address: 3098h base + 3h offset = 309Bh
Bit 7 6 5 4 3 2 1 0
Read SPRF SPMF SPTEF MODF 0
Write
Reset
0 0 1 0 0 0 0 0
SPI0_S field descriptions
Field Description
7
SPRF
SPI read buffer full flag
SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI
data (D) register. SPRF is cleared by reading SPRF while it is set and then reading the SPI data register.
0 No data available in the receive data buffer
1
Data available in the receive data buffer
6
SPMF
SPI match flag
SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the SPI_M
register. To clear the flag, read SPMF when it is set and then write a 1 to it.
0 Value in the receive data buffer does not match the value in the SPI_M register
1 Value in the receive data buffer matches the value in the SPI_M register
Table continues on the next page...
Register Definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
434 Freescale Semiconductor, Inc.