Datasheet

Address: 3098h base + 5h offset = 309Dh
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI0_D field descriptions
Field Description
7–0
Bits[7:0]
Data (low byte)
16.3.6 SPI match register (SPIx_M)
This register contains the hardware compare value. When the value received in the SPI
receive data buffer equals this hardware compare value, the SPI match flag (SPMF) sets.
Address: 3098h base + 7h offset = 309Fh
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI0_M field descriptions
Field Description
7–0
Bits[7:0]
Hardware compare value (low byte)
16.4 Functional Description
This section provides the functional description of the module.
16.4.1 General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.
While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI
function as:
• Slave select (SS)
• Serial clock (SPSCK)
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
436 Freescale Semiconductor, Inc.